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Principal Engineer - HBM PE Component Validation (Singapore) job at Micron, Singapore | WorkJio
Full-time Tech & engineering · Posted 20 Sept
Principal Engineer - HBM PE Component Validation (Singapore) M Micron From company site
Salary
Not stated by the company
Where
Singapore Fab 10A, Singapore
Start Not stated
Work mode On-site
Experience Experienced About the role A senior technical role owning complex validation scopes for next generation HBM products at Fab 10A. You will optimise test flows, lead technical problem solving, and mentor junior engineers while working with global teams. Suits an experienced validation or product engineer with deep platform, Verilog simulation and analysis expertise.
What you'll do Lead end-to-end validation run execution, keeping starts and completions on schedule and re-planning around risk Manage IQP/ETV material usage efficiently Own time-bound data crunching pipelines such as automated log parsing, metrics aggregation and anomaly ranking Know someone for this? Share it
Deliver decision-ready summary reports and sightings within agreed cycle time
Ensure coverage completeness across MBIST and flows, including Hot/Cold corners, TSV screen/AQLK and async timing boundary coverage
Develop and debug test programs on SM3/Cobra and Advantest V93K
Enforce code quality, reviews and release discipline
Align hardware configurations such as handler, socket, loadboard and probe card to test intent and throughput targets
Perform power and thermal characterization and correlate IDD/thermal data with performance and reliability
Author recommendations for content changes and silicon fixes
Architect and run Verilog simulations including bench creation, stimulus, checkers and waveform analysis
Build automation scripts and dashboards for anomaly detection, trend analysis and coverage auditing
Lead silicon debug across Design, Verification, Quality and System Engineering
Drive corrective action closure with clear root-cause evidence
Implement cycle-time optimisation strategies such as parallelisation, smarter sampling, content pruning and throughput tuning
Contribute to DFMEA gap closure and codify the definition of success for validation quality
Coach junior engineers on validation best practices, platform nuances, simulation methodology and reporting standards
Partner with global teams in Boise, Folsom, Hyderabad and Taiwan on material readiness and platform enablement
Apply AI to streamline workflows, optimise processes and support data-driven decision making Good to know Based at Fab 10A, Singapore Full time role Requirements Bachelor's or Master's in Electrical or Computer Engineering or a related field 10+ years in DRAM, HBM or NAND validation or product engineering At least 2 years of HBM validation experience Test platform code development in C/C++, Python and APG Strong expertise in MBIST (SM3/Cobra) and Mode (Advantest V93K) testing Verilog simulation expertise including bench architecture, stimulus/checkers, waveform and log analysis Apply on the company website
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Open application Listing ID 4878 · Report this listing
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