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About the role
This role sits with the NAND Product Reliability Architecture team at Micron's Fab 10N/X in Singapore. You will own the reliability architecture for the newest NAND products from end to end, shaping how qualification and stress strategies are built and how reliability algorithms and system features are integrated. It suits an experienced semiconductor reliability or product engineering professional who is comfortable influencing teams without direct authority and working at a fast pace.
What you'll do
Interpret internal, JEDEC and customer NAND reliability specifications so the qualification plan covers everything required.
Design end-to-end reliability qualification strategies for new products and technology generations, covering stress conditions, coverage models, sampling plans, readout points and acceptance criteria.
Compare specifications across product generations and application segments, spot gaps or unintended scope changes, and align with System and Quality teams.
Tune qualification sampling and flow coverage to cut cost and test time while keeping statistical confidence and customer protection.
Create and release reliability test flows across wafer-level and component-level platforms, readying them for new product and technology programs.
Keep reliability documentation and governance accurate, auditable and current for test methods, stress conditions and supporting capabilities.
Find and validate test-time reduction opportunities, quantify their value and prove them with data before production deployment.
Work with execution and operations teams to ensure clean implementation and on-time or accelerated qualification release.
Define architecture and integration strategy for new reliability algorithms, system features and product capabilities.
Drive system feature development with System Architecture, Design and Firmware teams by turning system-level requirements into component-level capability, setting validation criteria and confirming effectiveness before qualification use.
Develop, validate and deploy reliability-focused test capabilities, and support emulation, bench checkout, debugging and issue resolution with Design and Test Engineering teams.
Own technical execution from concept through validation, product introduction and sustaining support.
Lead investigation of reliability failures and qualification gating issues using structured problem solving, electrical characterization and physical failure analysis.
Link product-level failure signatures to device, process, circuit, firmware or system behaviour and turn findings into actionable mitigations.
Provide data-backed reliability positions for product changes, process changes, manufacturing excursions and customer-specific requirements.
Support customer inquiries and communicate technical findings, risk assessments and recommendations to engineering and leadership stakeholders.
Analyse large, high-dimensional reliability datasets such as thresh
Requirements
PhD, or Master's degree with at least 3 years, or Bachelor's degree with at least 5 years of relevant experience in Microelectronics, Materials Science, Physics or a related discipline
At least 5 years of relevant experience in semiconductor reliability, product engineering, test, design, validation or system media architecture
Solid understanding of non-volatile memory architecture and operation, including program, erase and read algorithms, threshold-voltage distributions, page and block structure and error-management concepts
Hands-on experience in semiconductor reliability, product engineering, test, design, validation, firmware, system development or a closely related domain
Experience in system feature development, including defining, developing, checking out and validating reliability-impacting features or algorithms, with understanding of how controller, firmware and system-level behaviour translate into component-level requirements
Demonstrated architecture development capability, including strategy definition, coverage modelling, sampling design and trade-off analysis across quality, risk and cost
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